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Lattice Semiconductor Corporation has released its third-generation high value FPGAs, the mid-range 65 nm LatticeECP3™ family. The LatticeECP3 FPGA family offers multi-protocol 3.2G SERDES with XAUI jitter compliance, DDR3 memory interfaces, powerful DSP capabilities, high-density on-chip memory and up to 149K LUTS, all with half the power consumption and half the price of competitive SERDES-capable FPGAs. The entire LatticeECP3 family is manufactured using Fujitsu's advanced low-power process technology, and is believed to be the only 65 nm mid-range, high-value FPGA family in the industry. The five devices that make up the low power LatticeECP3 FPGA family all offer standards-compliant, multi-protocol 3G SERDES, the industry's only DDR3 memory interface for low cost FPGAs and high performance, cascadable DSP slices that are suited for high performance RF, baseband and image signal processing. Toggling at 1 Gb/s, the LatticECP3 FPGAs also feature an ultra-fast LVDS I/O as well as embedded memory of up to 6.8 Mb. Logic density varies from 17K LUTs to 149K LUTs with up to 586 user I/Os.

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Lattice Semiconductor Corp.
http://www.latticesemi.com