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Lattice Semiconductor announces its ispLEVER™ 5.1 programmable logic design tool suite. Lattice FPGA logic utilization has been increased by as much as 35%, while design operating frequencies have been boosted up to 25%. An IP delivery infrastructure called IPexpress is included that allows designers to quickly configure Lattice system-level IP for their designs. The ispLEVER 5.1 software introduces a new FPGA design preference flow that gives more control to the designer. Design preferences that dictate how an FPGA design will be implemented in Lattice silicon are no longer tied to a particular stage in the design process. The FPGA designer can make changes to design preferences at any point, from the initial stage of HDL source code to final place and route, and is assured of greater consistency throughout the entire design process.

Lattice Semiconductor Corporation