IP Cores
Paxonet's cores are supported with evaluation boards and software drivers. All cores are re-targetable for design and implementation in FPGA (Altera and Xilinx), structured ASIC and cell-based ASIC methodologies in technologies ranging from 0.25um to 90nm and below. The company's IP portfolio ranges from SONET/SDH (155 Mbps to 10 Gbps), Ethernet (10 Mbps to 10 Gbps), PDH, Layer 2 processing, virtual concatenation and GFP. Paxonet also offers three standard variations of virtual concatenation technology. The first of these is HOVC-only (CC375 and CC377 for STS48/STM16 and CC475 STS192/STM64) for connecting Gigabit Ethernet, FibreChannel or similar networking protocols to high-speed SONET and SDH pipes. The second is a LOVC-only (CC376 for STS3/STM1 and STS12/STM4) version that is suitable for transport of 10/100 Ethernet in a mixed voice/data environment. The third variant is a combined HOVC and LOVC for STS48/STM16 highly integrated, aggregation applications. All these designs implement LCAS, so that bandwidth can be flexibly added and dropped from bundles as demanded by customer bandwidth needs or by network reconfigurations.
Paxonet Communications, Inc.
Paxonet Communications Inc.
45131 Manzanita Ct
Fremont, CA, 94539-6696
© 2008 Advantage Business Media
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