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Cambridge Consultants introduces a 16-bit RISC microprocessor IP core, which features a modern, high-performance RISC architecture with low gate count, low power consumption and high code density. It is optimized for use in cost- and performance-sensitive ASIC designs. On a 0.18 micron CMOS fabrication process, XAP4 can deliver up to 63 Dhrystone MIPS at a clock frequency of 117 MHz. This benchmark performance of 0.54 MIPS/MHz is a 50% improvement over the company’s previous 16-bit processor, XAP2. The device has both 16-bit data and address buses and is capable of running programs up to 64 Kbytes. The first implementation of the processor has a two-stage pipelined Von Neumann architecture. It is delivered to licensees as a soft IP core in Verilog RTL that can be synthesized in as few as 12 k gates for ASICs where die size and power consumption must be as small as possible. The processor core includes Cambridge Consultants' SIF debug logic, which provides full control over the processor and access to its debug registers, together with non-invasive access to any part of the processor's memory map for data acquisition while a system is running.

Cambridge Consultants