Meeting the Changing Power Management Requirements for Tomorrow’s Wireless System Designs
Advances in power management technology that support digital signal processing-based system requirements will be used in future wireless base station systems.
By Brian Narveson and Adrian Harris<
The need to create higher performance wireless systems in smaller form factors
has significantly increased the challenges for the power management designer.
Increasingly
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Figure 1. Typical DPA architecture |
designers are asked to provide more voltage rails for a variety of digital signal
processors (DSP), field programmable gate arrays (FPGA), application specific
integrated circuits (ASIC) and microprocessors. In short, they are required to
generate more voltages, at higher currents, more efficiently, with less noise
in a smaller space.
The driving requirements come from the need to design power systems for small
pole-mounted base stations for cellular voice, data and wireless fidelity (WiFi).
The driving factors are size, thermal management, cost and electrical performance
(regulation, transient response and noise generation). I will briefly discuss
advancements in each of these areas.
SIZE / EFFICIENCY / COST
The need to address size, efficiency and cost simultaneously has created a need
to take another look at power architectures. The first generation of base stations
used a power architecture known as distributed power architecture (DPA). An example
of the DPA is shown in Figure 1. This architecture used an isolated (brick) power
module for every voltage rail. It worked well when there were limited rails, but
cost and PC board space increase significantly with each added voltage rail. Sequencing
of the voltage rails was also difficult and required adding external circuitry,
which also added cost and board space.
To deal with the size and cost constraints of DPA, second generation systems moved
to a fixed-voltage intermediate bus architecture (IBA). An IBA (Figure 2) uses
a single isolated brick power module and many non-isolated point-of-load (POL)
DC/DC converters. The POLs can either be power modules, such as TI’s PTH series,
or discrete buck converters. The isolated converter works over the same input
voltage range as the first generation, either 36 V to 75 V or 18 V to 36 V. It
creates an intermediate bus that is regulated to 3.3 V, 5 V or 12 V. The voltage
choice is up to the system designer. This design results in less board space,
lower cost and easier sequencing of the voltages, due to features such as TI’s
Auto Track™. The only drawback of this architecture is reduced efficiency
due to the double conversion required for each voltage.
Initial third-generation (3G) systems continued to use fixed voltage IBA. But
as micro-cell base station designs evolved to sealed enclosures with no forced
air cooling, it created a need for a higher efficiency and smaller footprint solution.
As every designer knows, the best way to get rid of heat in a system is to not
create it. Since all of the
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Figure 2. Fixed voltage intermediate bus architecture |
power goes through the front end isolated converter, it is the main focus when
looking for efficiency improvement. The proven way to increase isolated converter
efficiency is to run it at a fixed duty cycle and not regulate the output. That
led to the unregulated intermediate bus architecture (Figure 3). This architecture
uses a unregulated bus converter where the output voltage is a ratio of the input
voltage. In the example, an ALD17 5:1 converter creates an output voltage that
is one-fifth of the input. This technique creates a design where a 150 W system
can now be designed with a one-sixteenth brick and achieve 96 percent efficiency
for the first conversion stage. Use of this unregulated voltage became possible
with the introduction of wide input (4.5 V to 14 V) PWMs and power modules such
as TI’s T2 products. The limitation of this architecture is the maximum input
range of the bus converters is 36 V to 55 V. This is necessary to keep the input
voltage to POLs less that 12 V. The 12 V maximum is necessary because for POLs
to generate 1V or less output voltages, the input voltage cannot exceed 10 to
12 times the output. However, an increasing number of base station original equipment
manufacturers (OEM) are considering a move to this limited input range. That is
due to the significant cost savings, size reduction and efficiency improvements
obtained with this architecture.
Some wireless providers are insisting on maintaining the traditional wider input
voltage specification of 36 V to 75 V with input transients to 100 V. For these
requirements, the power industry has responded with the quasi-regulated IBA (Figure
4). The main difference from this and the unregulated IBA is that if the input
voltage exceeds 55 V to 60 V, the output voltage is regulated to around 10 V.
The drawback of this approach is that the isolated power module must increase
in size to accommodate the regulation circuitry, and its efficiency is reduced
above 55 V. An example of this kind of product is the TI PTQB series.
In order to provide a meaningful comparison, the example in each figure has identical
voltage and current requirements. It is based on a theoretical base station utilizing
multiple high performance DSPs with associated analog and digital circuits. The
output voltages are 3.3 V at 5 A, 2.5 V at 6.5 A, 1.8 V at 11 A and 1.2 V at 20
A. A comparison of the architectures described above is shown in Figure 5. The
graphs indicate that the ultimate dream is indeed possible. A quasi-regulated
or unregulated power system can provide higher efficiency, in less space - and
at lower cost. The most notable improvement from the second generation fixed IBA
to the quasi/unregulated IBA is efficiency. As can be seen in Figure 5, the power
conversion efficiency increased almost seven percent. This translates to a thermal
load reduction of 14 W for a 200 W system.
We used power modules in these examples because they provide the greatest power
density, and are the solution of choice at leading base station OEMs. Pricing
for POLs is based on 1K distributor pricing, OEM pricing would be less.
ELECTRICAL PERFORMANCE
The remaining challenge is for the designer is to meet the increasing electrical
demands at the heart of each system — high performance DSPs and ASICs. The
primary
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Figure 3. Unregulated intermediate bus architecture |
performance issues are voltage regulation, current transient response and noise.
Regulation and current transient response are closely linked. In order to get
higher performance, with lower power in a smaller size, digital semiconductors
are fabricated with smaller geometry transistors that require ever decreasing
voltages. Sub-1V core voltage requirements are now becoming the standard. Along
with this low voltage have come increasingly tighter tolerances. It is now common
practice to specify a total voltage tolerance of three percent including line
(variations in input voltage), load (small deviation in load current), time, temperature
and current transients. This leaves the power designer with only 30mv of head
to accommodate everything the digital guys throw at him. About half of the tolerance
budget (15mv) is usually absorbed for the DC parameters of line, load, time and
temperature. The remaining 15mv is then available to deal with sudden (1-3 clock
cycles) current changes in current due to computational or data transmissions
loads.
This creates power system design challenges to minimize voltage deviation in the
presence of these current transients. If the core voltage (VCC) exceeds the specified
tolerance limits, the digital IC may initiate a reset or have logic errors. To
prevent this occurrence, designers need to pay close attention to the transient
performance of the POL modules they are using. Digital loads, such as the latest
Gigahertz DSPs, require extremely fast transient responses with very low voltage
deviation. To achieve these targets, many additional output capacitors are usually
added to the
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Figure 4. Quasi-regulated intermediate bus architecture |
DC/DC converter to provide hold-up time until its feedback loop can respond. The
power module, including this added capacitance to meet transient voltage tolerances,
represents the complete power solution.
Capacitors have been evolving over the years, with volumetric efficiencies getting better all the time. Even with higher volumetric efficiency, the overall power solution can be over twice the size of the power module alone. This requires a large printed circuit board (PCB) allocation that is usually not available in micro base stations. What’s more, the bill of material (BOM) costs of Vcc power can be more than double the cost of the power module when adding in the cost of capacitors.
With innovations in DC/DC power module technology, system designers are now able
to achieve faster transient response and less voltage deviation using less output
capacitance. An example is the T2 series next generation PTH modules
from Texas Instruments. These devices incorporate a new feature called TurboTranstm
technology. This patented technology allows the designer to custom tune the module
to meet a specific transient load requirement. Tuning is accomplished with a single
external resistor.
TurboTrans can achieve up to an eight-times reduction in output capacitance. The
feature saves the cost of capacitors and PCB space.
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Figure 5. Comparison of architectures |
Another benefit of this technology is enhanced stability with ultra-low equivalent
series resistance (ESR) capacitors. Designers can use newer Oscon, polymer tantalums
or all ceramic output capacitors without stability concerns. This allows use of
capacitor technologies capable of withstanding high temperature, lead-free solder
profiles.
The final performance hurdle for isolated and POL converters is noise. When switching POLs run at different frequencies and share a common input bus, frequencies resulting from the sum and difference of those frequencies can create beat frequencies that make EMI filtering difficult. As an example, if a system has two POLs with one operating at 300 kHz and a second at 301 kHz, the beat frequency is 1 kHz. This can require larger more complex system filters. TI’s T2 power modules have a SmartSync feature that allows the designer to synchronize the switching frequency of multiple T2 modules to a specific frequency. Synchronized modules eliminate beat frequencies and make EMI filtering easier. SmartSync can be used to set the frequency so switching noise is out of a particular frequency band (i.e., the IF frequency of a receiver). TurboTrans and Smart Sync are standard features on T2 power modules that add no additional system cost to the systems described earlier.
A system built with state-of-the-art power modules will allow system designer to reduce system size, decrease dissipated power, meet the power demands of high-performance digital circuits and reduce the cost of power compared to second generation systems.
About the Author
Brian C. Narveson is a Senior Member of the Technical Staff and Manager of
the Power Market Development md - High Performance Analog Group at Texas Instruments
(TI). Prior to the acquisition by TI in 1999, he was Vice President of Engineering
for Power Trends.
Adrian Harris is an Application Specialist with the Plug-In Power – High Performance Analog Group at Texas Instruments. Adrian can be reached at ti_adrianharris@ti.com.
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