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To deliver innovative products on time, engineers need automated verification process management, IP reuse and the latest verification methodologies. The Cadence® SoC Functional Verification Kit provides high levels of automation with reusable advanced verification techniques. It interactively integrates with the company’s Incisive® Plan-to-Closure Methodology, reducing risk and delivering more efficient verification planning and execution. Now design and verification teams can implement a proven methodology using an interactive flow-based approach. Rather than providing verification point-tools in isolation, the kit delivers a combination of best-known principles, practices, and procedures — using all aspects of the Incisive functional verification platform. More than just a static paper snapshot of methodology, the Cadence SoC Functional Verification Kit is highly interactive with its own GUI navigator to jump-start the process by demonstrating how experts in verification developed and implemented advanced coverage-driven techniques. It's also modular, allowing companies to adopt the methodologies incrementally and focus only on the most critical portions of the project. The kit addresses the verification of both hardware and software from block to chip to system levels, and low-power functional verification of the RTL. It guides engineers down a streamlined path from verification planning to closure.

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