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Cadence announced its next-generation Incisive Palladium II acceleration/emulation system that delivers up to twice the speed and capacity of the first-generation Palladium system. The Palladium II system is targeted at designers verifying the most complex system-on-chips (SoCs) in the wireless, networking, computing, and multimedia markets. The Palladium II system achieves reaches 256 million-gate capacity and is one-third the size of the first-generation system. Teams can develop and fully verify embedded systems software before receiving first silicon, thereby helping shrink the development cycle. In addition, verifying software prior to silicon tapeout enables designers to find bugs that can be fixed optimally in silicon, as opposed to attempting to "patch" the software at a later date. The Palladium II accelerator/emulator allows target connections of up to 61,440 I/Os, enabling verification of a full system or multiple chips running in parallel. In addition, the multi-user mode can support up to 32 users independently running both in-circuit emulation and simulation acceleration. The system allows multiple users to access and verify multiple pieces of their hardware and software code, run regression tests or validate different blocks of their design. The optional remote access feature allows users in multiple locations to collaborate or work separately on various blocks or designs.

Cadence Design Systems, Inc.

Cadence Design Systems
Public Relations
2655 Seely Ave.
San Jose, CA, 95134