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Texas Instruments announces the third generation of its discrete PCI Express physical layer (PHY) chip. The device, designed for flexibility and space savings, is targeted at interfacing with ASICs as well as low cost FPGAs in PC add-in cards, communications, test equipment, servers and other embedded system applications. TI has designed the new PHY to be compliant to PCI Express 1.1 specifications, which is critical for interoperability with other PCI Express applications. The TI PCI Express PHY gives board designers flexibility by offering both an 8 bit and 16 bit interface. The interface also is based on the PHY Interface for the PCI Express (PIPE) Architecture version 1.0 from Intel, with minor enhancements that allow for lower power consumption and a simplified interface for easy integration.

Texas Instruments