| Glossary
of Acronyms
AMS — Analog/Mixed-signal
Simulation
BiCMOS — Bipolar Complementary Metal-oxide Semiconductor
IC — Integrated Circuit
I/O — Input/Output
IP — Intellectual Property
POR — Power On Reset
RTL — Real-Time Logic
SMBus — System Management Bus
SOC — System-On-a-Chip
SPICE — Simulation Program with Integrated Circuit Emphasis
UVLO — Under Voltage Lock Out
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Designers now require a design methology that can supply a unified approach to system and circuit design. Verilog-AMS is one solution that gets the job done.
By J. G. Mena, R. Cooper, H. Schmeller, H. Deng, R. Stair and D. Ramamurthy
Portable power integrated circuits commonly have been placed into two categories: analog dominated products such as battery chargers or buck/boost converters, and digital dominated products such as battery gas gauges. Dividing products this way allowed designers to stay either in the analog or digital world without requiring the ability for mixed-signal IC design flow.
click the image to enlarge
Figure
1. Notebook computer battery charger block diagram.
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Product demand has its way, though, and now IC development groups must look for
a new design and verification flow that can handle complex mixed signal IC designs
to meet the requirement for complete SOC for power management applications with
extensive digital control. And, not only has product complexity increased, but
so has the pressure to reduce the time to market. Therefore, a big part of the
new design flow was to reduce overall project cycle time.
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Figure 2. Simplified block diagram for the converter core.
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Two methods reduce project cycle time for complex SOCs. First, the design flow
uses a verification tool to speed fast mixed signal top-level simulation cycles
with acceptable accuracy for analog circuits. Secondly, the design flow offers
a better way to hand off the product from the system definition to the IC design
team. Because software platforms differ, there was no direct software interface
between systems and IC design other than the device specification. When both
system level designers and IC level designers use the same software tools, system
defined test benches or system components can be reused, and misunderstandings
between systems and design groups are reduced.
Portable Power Applications
Today's portable power management ICs
integrate more and more features to be competitive. For the discussion herein
a battery charger IC for notebook computers is referenced, but the design methology
applies to any number of circuits in any number of industries.
The battery charger IC may integrate a communications interface for a microcontroller,
power path management, and various functions for charge control, as well as
a DC/DC converter to charge the battery. An example of this type of charger
is shown in Figure 1.
Achieving adequate top-level simulation coverage of these highly integrated power management ICs has been an elusive, if not unattainable goal for designers. For notebook computer battery chargers, the DC/DC converter switching frequencies can reach the MHz range, and comparator deglitch times may be on the order of tens of ms. This wide range of frequencies makes real-time top-level chip simulation virtually impossible.
Designers frequently resort to modifying schematics to evaluate the effects of a deglitched comparator changing states. This is an overhead for designers, because additional work is required to create modified versions of cells specifically for top level simulation, and also because the data heading to the mask shop does not exactly represent what has been simulated. Although much advancement in simulation technology is needed before designers can fully simulate a complex top-level chip, certain measures can be taken to reduce errors and improve simulation time.
This latest generation of development tools works well for the mixed signal simulation of complex mixed-signal ICs that integrate large amounts of digital content with high-performance analog circuits. But the simulation tool is only a part of the solution. With these complex mixed-signal ships, it is critical to partition the design such that all (or nearly all) of the digital content is contained in a single cell, or branch of hierarchy, at the top level. It is also best if the digital section of the chip can be coded in RTL. Top-level analog blocks can then be simulated either at the transistor level or using an AMS model, depending on the desired accuracy and simulation time. The goal is to get a modularized top-level design, in which block views can be substituted in and out between RTL, AMS, and transistor level, depending on the desired accuracy/speed tradeoff.
Converter System Design and Verification
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Figure 2. Simplified block diagram for the converter core.
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The main analog section of the notebook computer battery charger is the synchronous converter. This buck converter is the core of the switching charger system. The proposed unified circuit and system design flow was applied to the design of a buck converter (Figure 2 is the simplified block diagram of the entire buck converter).
A voltage control loop inside the converter is composed of the power stage, voltage feedback, error amplifier, logic, level shifter and driver. Some additional blocks such as bandgap reference, UVLO, thermal protection, POR and soft start are included in this converter. All of these blocks make the converter a large analog system. To verify the system performance, a long simulation time is generally required.
For example, to simulate the converter's transient response, the converter
first must be powered up. After it goes into steady state, the load current
will step up or step down to generate a voltage error at the output voltage.
The process takes 3 to 4 ms. It takes a long time to verify the performance
of the whole converter based on transistor-level simulation, and sometimes
verification it is impractical because of the time required. A fast simulation
method for the design and verification of this system would save development
cost and help to reduce some design risks.
Because the switching charger is a mixed-signal system with analog and digital parts, a mixed-signal simulation environment is required for top-level verification. To speed the verification of the buck converter and sustain compatibility with top-level verification, some Verilog-AMS behavioral models for sub-blocks such as the PWM converter, error amplifier, oscillator, and current sensor were developed.
The simulations based on behavioral models were done first to functionally
verify the whole system. Once the system design and verification were completed,
transistor level circuits of the sub-blocks were developed. When the transistor
level circuit of one block has been developed, the behavioral model of that
block is replaced with the real transistor circuit in the whole system, and
the simulation based on the whole converter is done to verify that block's
functionality. In this way, blocks can be verified one-by-one in a short
time.
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Figure 3. Simulation results comparison
(a) blue: behavioral model and (b) red: transistor level.
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Figure 3 shows the comparison of the power-up simulation results based on AMS behavioral models and transistor level simulation. The simulation results shown in this figure indicate the behavioral models match the transistor-level simulation well. However, the computer time used for the AMS behavioral simulation is drastically less than the time required for the transistor-level simulation, and this reduced simulation time enables a fast verification of this complex system. AMS simulation accuracy depends on the modeling of the AMS models for the blocks.
As a sub-block of the switching charger system, the buck converter is inserted into the complete system. To verify connectivity between the converter and other chip sections, the behavioral model of the complete buck converter is used in the initial top-level simulation. This method saves significant time in the simulation verification phase of the development. Because all of the sub-block simulations and top-level simulations are based on the same platform, the behavioral model and test bench can be re-used throughout the entire design.
Top-level Verification
As all of the major sub-blocks of the chip are completed, it is necessary to verify the final functionality of the top-level chip. To verify a large piece of mixed-signal IP, many top-level tests must be run, each focusing on different test conditions, stimuli and outputs. Thus, it is important to offer different levels of abstraction for every block in the design. This approach enables the designer to selectively replace certain blocks with a detailed description or a complex model and rerun the same top-level tests, significantly reducing the cycle time for mixed-signal IP.
Architectural Trade-offs
To efficiently use a mixed-signal simulation and design environment, a proper design partitioning method is important. When creating behavioral models for blocks, which are used to switch views for top-level simulations, it is important to decide how much detail should be modeled for each block. This decision should be made at the beginning of the design cycle. For example, if a bias block is included as part of any common analog circuit, the behavioral model of the analog circuit can include bias currents and bias checks inside it to comprehensively model the circuit rather than having stray transistors outside the block to provide bias for the circuit. Planning for the levels of abstraction at the beginning of the design makes it easier to switch between views of the design during the top-level simulations.
Functional Simulations (Behavioral Models/Mixed-mode Simulations)
The configuration of the battery switch-mode charger is made up of a core logic block surrounded by all the core analog blocks such as reference, comparator and converter. Most of the key analog blocks were modeled at multiple levels. A level 0 model that carried correct pinout of that block and minimum functionality required for operation and a level 1 model that carried more detailed behavior and functionality for all the I/O pins was modeled. Note that for a level 0 model it is not necessary to model behavior for all the pinouts. For example, an oscillator could have a simple level 0 model just describing functionality, and a level 1 model would incorporate input bias currents, bias enable checks, trim bits, frequency dependence on trim and temperature.
Most of these analog blocks have a few enable and control input signals coming in from the digital core, and maybe even some signals fed back to the digital block. This is where it becomes advantageous to use the Verilog-AMS language. The enable/control I/O signals of the analog signals that reference to the digital core are modeled as logic pins and not as analog pins. This moves a lot of functionality into the digital solver/simulator thereby gaining simulation advantage. Because there are multiple supply voltages and thresholds for analog and digital, the level-shifters between logic and analog are also easily modeled to facilitate signal pass-through or blocking based on a ramping power supply.
The communication interface used in the switch-mode charger is an SMBus interface. A behavioral model for the SMBus interface was used as a tester to communicate to the chip. This communication is bi-directional. Because Verilog-AMS supports bi-directional interface elements, it was possible to drive the SMBus tester directly into analog portions of the chip without any problems. Once the RTL for the logic core, the SMBus tester and the behavioral models for the analog blocks (level 0 or level 1) were ready, it was possible to do a lot of mixed-mode top level simulations using the same SMBus tester used for testing the RTL of the logic core along with the analog blocks in the environment.
This facilitates discovery of a lot of logic/analog interface problems and functional bugs early in the design cycle. Then the same test environment can be reused again and again when detailed analog blocks are ready to make sure the transistor level blocks also meet the specifications in the same manner.
click the image to enlarge
Figure 4. Mixed mode simulation results for
the charger portion of the IC. /CHGEN is the external stimulus used
to enable and disable charge, EAO is the output of the error amplifier,
SRP — SRN is the regulated charge current, and BAT is the charger
output voltage. In this simulation there is a 1Ω resistor in
series with the battery.
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Experimental Results
The switching battery charger was fabricated
in a 0.35µm BiCMOS technology. First silicon was fully functional. The
high quality of first silicon was the result of a comprehensive top-level verification
strategy using a mixed-signal design environment, which can be shared by system
level designers and IC designers. The total IC design cycle time was drastically
reduced because of the flexibility the new design environment offered.
Figures 4 and 5 show the behavior of the IC as charge is enabled and disabled
via the external CHGEN pin. Figure 4 shows results of the mixed signal simulation,
which used behavioral models for the logic portion of the IC, the ramp generator
and the oscillators. Figure 5 shows experimental results for the device under
similar operating conditions. These figures show that mixed-mode simulations
accurately predicted the behavior of actual silicon.
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Figure 5. Experimental results with the same
conditions as in Figure 4.
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Summary
A new portable power IC verification approach based on a unified design environment using Verilog-AMS mixed signal simulation was successfully used to design a mixed mode switching charger system. Experimental results and comparisons between simulation and test demonstrated the advantages of this new approach.
Compared to a traditional verification method based on SPICE simulation, this approach provides mixed abstract level, mixed-signal simulation capability and a reduced IC design cycle. A unified environment for both system and transistor level design and verification makes it possible to reuse the test benches from system level design at the transistor level, which simplifies the design transformation from system level to transistor level and reduces design time and design risk.
Acknowledgment
Thanks to Raji Gurumurthy and Wei Zhang for their contribution to the new AMS design environment for power IC design. We also thank Scott Eisenhart for encouragement and advice, and Keith Droge and Mike Meeds for support during the development of the new design environment.
About the Authors
Diwakar Ramamurthy is an Applications Engineer at Cadence Design Systems. He
works with Texas Instruments in the Analog/Mixed-Signal Products area. His areas
of interest are in Simulation and Verification, Top-Down Design and behavioral
modeling of complex Analog/Mixed-Signal SOCs.
Jose G. Mena received the B.S.E.E. degree in 1975 from the Universidad Central
de Venezuela, Caracas, Venezuela, and the M.A.Sc. and Ph.D. degrees in electrical
engineering from the University of Toronto, Toronto, Ontario, Canada, in 1981
and 1985, respectively. From 1975 to 1978, he worked at the integrated circuits
laboratory of the Venezuelan Institute of Scientific Research (IVIC), Caracas,
Venezuela. From 1985 to 2003, he was employed at AT&T Bell Laboratories/Lucent
Technologies/Agere Systems as a member of Technical Staff/Technical Manager.
In 2003, he joined Texas Instruments as a Design Manager responsible for the
design and development of linear and switching chargers, power management ICs,
gas gauges and analog front-end products
References
1. Deng, Haifei; "Design and verification of Synchronous Buck Converter"; Private
communication; December 8, 2004.
2. Gurumurthy, Raji; "Analog Mixed-Signal Design Environment"; Private communication; December 8, 2004.
3. Mena, Jose G.; Randall Cooper; Diwakar Ramamurthy; Analog Mixed-Signal Design Overview" Seminar, June 18, 2004.
Texas Instruments Inc.
Semiconductor Group SC-98054
4500 Cambridge
Fort Worth, TX, 76155
