Designing for Low Power with DSPs
Today's DSPs are the ideal platform for low
power designs, regularly offering 90% or more in power
savings.
By Leon Adams and Raj Agrawala
Glossary of acronyms
ADC — Analog-to-Digital Converter
API — Application Program Interface
BIOS — Basic Input Output System
CMOS — Complementary Metal Oxide Semiconductor
CPU — Central Processing Unit
DMA — Direct Memory Access
DSP — Digital Signal Processing
GPS — Global Positioning System
I/O — Input/Output
MMC/SD — Multimedia Card/Secure Digital
PSL — Power Scaling Library
PWRM — Power Manager
RTOS — Real-Time Operating System
SRAM — Static Random Access Memory
SDRAM — Synchronous Dynamic Random Access Memory
USB — Universal Serial Bus
V/F — Voltage and Frequency
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Power efficiency is an increasingly important requirement across a broad range of DSP systems, often differentiating a product against its competition. For mobile devices, power efficiency not only means a longer time between battery recharges, but also allows the use of smaller batteries and possibly an advanced battery technology, with a corresponding reduction in product size and/or cost.
Power efficiency also can allow an increase in component density, resulting in increased capacity of channels, reduction of product cost or both.
Power efficiency is determined not only by hardware design and component choice, but also by software-based, runtime power management techniques. For DSP system designers, the key to making intelligent hardware choices and using power management software effectively depends on obtaining information about power consumption during operation, then controlling power supply to the various DSP and system functions. But DSP power information and control traditionally have focused on typical core and memory consumption, ignoring important factors such as operating modes, peripherals and I/O load. The lack of information and control over power consumption in these areas imposes a significant handicap on system designers as they work to optimize their systems.
A power perspective for the complete chip provides more granular control of the power domain in the device and extends it to more functions. The complete-chip perspective also includes tools for system power planning and analysis, along with power saving implementation software and support. Several relatively new DSPs include these features. The results are significant, with a reduction in application power consumption of 90% or more. The combination of high performance and low power offered by these DSPs will extend the operational life and functionality of a wide variety of handheld and infrastructure systems for communications, entertainment, instrumentation and other application areas.
Active & Static Power Consumption
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Figure 1. Power manager partitioning. The PWRM is designed for efficiency, flexibility and loose coupling to the operating system.s
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Power consumption occurs both when the system is switching from one logic state to another, or is active, and when it is not switching, or is static. Traditionally, CMOS static power consumption, because of leakage through the transistors, has been negligible when compared to active power. However, the latest CMOS processes create smaller, higher-performance transistors running at extremely low voltages that minimize CPU active power consumption. However, the cost of this is proportionately greater leakage currents, thereby increasing standby (leakage) power.
Application execution operating modes, peripherals and I/O load play significant roles in determining total DSP system-level power consumption for battery-powered products. However, these realities are all but ignored by the traditional DSP focus on the processor core and memory power as measured in mA/MHz. In order to maximize power efficiency for a specific end-user product, a complete-chip power perspective must take into account the core and memory power, as well as provide innovations in chip design to manage peripheral and I/O power to extend the idle power domain.
Today’s designs require attention be paid to reducing static as well as active power consumption beyond the CPU into peripherals and I/O. For instance, some of the new 1.2 V DSPs feature standby power consumption of 0.12 m. This is less than 1% of the standby power required by previously available devices. At the same time, active power required by the core and memory is also kept extremely low. One design has achieved a 58 mW at 108 MHz result by minimizing all aspects of power consumption. Further, significant capability to turn peripheral power off and on as needed saves operating power.
Reducing static power consumption is particularly important in systems such as wireless phones and portable data terminals, which often remain in standby mode much longer than for active communication. Also, being able to idle and eliminate power from peripherals that are not in use, such as USB connections, can save operating power of products like mobile jukeboxes. Different systems have different power consumption profiles, because the pattern of switching between active and standby modes is unique for each. System optimization requires tools that give the designer visibility into power consumption over time and during different operating modes. In addition to visibility, designers also need the means for dynamically controlling power consumption by changing function modes through software as system operation changes.
Designing Chips for
Power Conservation
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Recognizing these needs, DSP vendors have introduced a number of important power reduction techniques into products designed for mobility. Manufacturing processes now allow chip designers to power-tune the device by using low voltage, low-leakage transistors, for example.
Relatively new introductions provide different sizes of on-chip SRAMs to help designers optimize power consumption by right-sizing memory size to fit their application. That is, if code can execute from on-chip memory instead of off-chip memory, significant amounts of power burned in memory interface logic and I/O drive used to read from, and especially write to off-chip memory can be saved.
Although exact memory requirements vary with individual implementations, DSPs with 64 kB of on-chip SRAM tend to work well for applications such as biometric instruments, 128 kB for wireless radio and GPS and 256 kB for portable multimedia and communications. In keeping with application focus, devices with higher memory levels often add USB 2.0 support and ADCs for greater I/O flexibility, as well as MMC/SD ports for memory card support.
Power Reduction Techniques
These power-saving features, inherent in the hardware operation, are complemented by other techniques that can provide significant reduction in active power consumption at run time. Among these techniques are clock idling, power rail gating and V/F scaling.
One of the simplest ways to save on active power consumption is to stop clocking a circuit to idle it when it is not needed. Most processors incorporate a mechanism to temporarily suspend the core while waiting for an external event, but a few go further by supporting the selective idling of multiple, individual clock domains. Separate clock domains may be selectively gated ON/OFF as needed for the core, cache, DMA, clock generator, peripherals and external memory interface. The latency to idle and wake the circuit is typically manageable within the application, which needs to be able to save power but also meet real-time performance needs.
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Figure 2. DSP power spreadsheet. For access to this spreadsheet, please visit: www.ti.com/powerspreadsheet.
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DSP system power planning and analysis tools, plus power-saving implementation software and support, are also necessary to provide essential optimization information and control for the system designer. Software-controlled modes that clock only those functions required for a specific operation can simplify control and provide further refinement on power savings. Hardware can be supported by multiple standby modes that permit the designer to clock functions on and off selectively. Power savings in operation can also be augmented through control in the boot sequence, keeping unused functions off during system start-up, instead of following the usual practice of bringing all functions to a power-up state initially.
Finally, if a DSP can reduce the core clock rate and still meet its processing requirements, it can have a proportional savings in active power consumption. If the lower frequency is compatible with a lower operating voltage available to the core, then a significant additional savings can occur. DSPs that are designed to support scaled voltages and frequencies through dynamic interaction with software provide an important means for cutting power consumption during off-peak processing intervals.
RTOS Power Management
Increasingly, systems are being assembled with programmable processors using software components from multiple sources. Clock idling, dynamic frequency and voltage scaling can have a significant effect upon these components and the operating system itself. For example, idling clocks independently by application threads could easily lead to deadlocks and missed deadlines. Frequency scaling could disrupt the RTOS time services, execution of periodic functions and API timeouts, as well as the application’s ability to meet its real-time deadlines. Device drivers often need to be notified of frequency changes and sleep states so that they can reset registers and command external devices to low-power states.
An example of implementation for power management control is the DSP/BIOS RTOS for certain new DSPs. These devices implement power awareness and control through a PWRM that supports preemptive threads with priority scheduling for tasks and software and hardware interrupts. The PWRM provides power management techniques in such a way that application developers can easily pick and choose among them for specific applications. Supported techniques include clock idling, voltage/frequency scaling, frequency-only scaling and available chip sleep modes.
The PWRM is designed for efficiency, flexibility and loose coupling to the operating system itself, as shown in Figure 1. It does not exist as another task in the system, but as a set of APIs that execute in the context of application control threads and device drivers. The PWRM interfaces directly to the DSP hardware by writing and reading a clock idle configuration register, and through a platform-specific PSL that controls the core clock rate and voltage-regulation circuitry. The PSL supports callbacks to application code before and after scaling and supports query operations to determine current voltage and frequency, supported frequencies and scaling latencies. In this way, the PSL isolates the PWRM and the rest of the application from the low-level implementation details of the frequency and voltage control hardware.
The role of the PWRM is to manage all things power-related in the DSP/BIOS application, both statically configured by the application developer and dynamically called at run time by the application. Interfaces to the PWRM allow the application developer to selectively idle clock domains, specify a power-saving function to be called at boot time to turn off unnecessary resources, dynamically change voltage and frequency at run time, activate chip-specific and custom sleep modes and provide central registration and notification of power events to system functions and applications.
Power Measurement
The usefulness of all these power saving techniques requires visibility into operational power consumption through tools such as the LabView-based Power Measurement tool, which is designed for connection to a developer’s target hardware, or an available DSP-based evaluation module. The tool enables developers to measure, visualize and analyze DSP chip net power consumption. Tabular and graphical views display power data over time and allow developers to compare the planned power budget versus actual power consumption.
Planning for system power requires careful estimation of the requirements of different functions over time, supplied by documents such as application notes and spreadsheets that give detailed power consumption data for a DSP’s internal functional units and peripherals. Using this information, developers can create trial configurations to estimate power requirements for various combinations of memory and peripherals. Figure 2 shows the detail of information available through an example spreadsheet for determining DSP power requirements.
Audio Example
A benchmarked application example shows how effective these power savings techniques can be, with active power reduction exceeding 90%. While this example uses a TI DSP, similar results can be expected with comparable DSPs.
Test and Results
A working audio application was tested by modifying it in steps and gauging the payoff as different power saving features were turned on. The application used DMA to move audio data samples in and out of the DSP from a stereo codec via on-chip multichannel buffered serial ports. A pair of speakers served as the output. The following changes were made in the order presented, and the modification in power consumption was observed. Table 1 summarizes the power measurements observed.
• Operate the application with no power savings features enabled. In this mode, the DSP core was using 209 mW to playback audio.
• Configure the Power Manager to be ON and enable idling of the core and cache in the RTOS idle loop, reducing core and memory power consumption by 32%.
• Step down the frequency in accordance with the setpoints configured in the PSL. No audio degradation was observed down to 24 MHz, at which frequency power consumption dropped by 85%.
• Combine DSP core and cache idling in the RTOS idle loop with the frequency scaled to 24 MHz, lowering power consumption by another 4%.
• Add in voltage scaling along with the frequency scaling. Power consumption fell to 9.59 mW, a 95% reduction overall, with no degradation in audio quality.
• Measure static (standby) power consumption when the DSP was put into deep sleep while waiting for an external application interrupt.
In addition to these steps, a boot function was configured to turn off certain board features and clocks at boot time, including the audio codec, which was later powered back up when the device driver was opened. The registration and notification mechanism was also used to put the codec into its low power mode when the DSP went into deep sleep.
Conclusion
New complete-chip perspectives on power control are extending advanced techniques for DSP power savings even further. Improved DSP chip hardware with low standby power, right-sizing of on-chip SRAM for application needs, clock idling, voltage and frequency scaling and power measurement and planning tools are chief among the many innovations being offered to system designers to help plan and achieve lower application power consumption. Just as important, complementary software innovations make it possible to scale operating frequency and voltage and manage clock idling of peripherals dynamically through software control, even in complex systems that must support multiple tasks. All of these techniques will help save power in mobile systems, extending DSP performance to new application areas.
WD&D
References
Benini, Luca, and Giovanni DeMicheli, System-Level Power Optimization: Techniques and Tools, ISLPED99, 1999.
Cryan, Rob, Using the Power Scaling Library on the TMS320C5510, SPRA848; Texas Instruments.
Gary, Scott, “Power-Optimizing Embedded Applications,” Proceedings of the Embedded Systems Conference, March 2004.
Reference Frameworks for eXpressDSP Software: RF5, An Extensive, High-Density System, SPRA795, Texas Instruments.
TMS320C5000 DSP/BIOS Application Programming Interface (API) Reference Guide, SPRA404G, Texas Instruments.
TMS320 DSP/BIOS User’s Guide, SPRU423E, Texas Instruments.
Verret, Ryan. TMS320VC5510 Power Consumption Summary, SPRA972.
About the Authors
Leon Adams and Raj Agrawala are employed by Texas Instruments, Stafford, TX. Adams can be reached at 281-274-2273 and leonadams@ti.com; Agrawala can be reached at 281-274-4172 and ragrawala@ti.com.
Texas Instruments Inc.
Semiconductor Group SC-98054
4500 Cambridge
Fort Worth, TX, 76155
© 2008 Advantage Business Media
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