Low-Power, High-Value FPGA Devices
Lattice Semiconductor Corporation has released its third-generation high-value FPGAs, the mid-range 65 nm LatticeECP3™ family. The LatticeECP3 FPGA family offers multi-protocol 3.2G SERDES with XAUI jitter compliance, DDR3 memory interfaces, powerful DSP capabilities, high-density on-chip memory and up to 149K LUTS, all with half the power consumption and half the price of competitive SERDES-capable FPGAs. The entire LatticeECP3 family is manufactured using Fujitsu's advanced low-power process technology, and is believed to be the only 65 nm mid-range, high-value FPGA family in the industry.
"Like our award winning LatticeECP2M™ devices before it, our LatticeECP3 family once again redefines mid-range, value-based FPGAs, not only by further reducing costs, but also by reducing static power consumption by 80% and total power consumption by over 50% for typical designs, compared to competitive SERDES-
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capable FPGAs. By making careful design choices and minimizing die size, we are able to offer designers the benefits of high speed serial I/O and processing capabilities, without the power and cost premiums typically associated with these types of devices," said Sean Riley, corporate vice president and general manager of High Density Solutions.
The five devices that make up the low power LatticeECP3 FPGA family all offer standards-compliant, multi-protocol 3G SERDES, the industry's only DDR3 memory interface for low cost FPGAs and high performance, cascadable DSP slices that are suited for high performance RF, baseband and image signal processing. Toggling at 1 Gb/s, the LatticECP3 FPGAs also feature an ultra-fast LVDS I/O as well as embedded memory of up to 6.8 Mb. Logic density varies from 17K LUTs to 149K LUTs with up to 586 user I/Os. The LatticeECP3 FPGA family's high performance features include:
• 3.2G Gbps SERDES with 10GbE XAUI jitter compliance and the ability to mix and match multiple protocols on each SERDES quad. This includes PCI Express, CPRI, OBSAI, XAUI, Serial RapidIO and Gigabit Ethernet.
• The SERDES/PCS blocks have been designed specifically to enable the design of the low latency variation CPRI links that are found in wireless basestations with Remote Radio Head connectivity.
• Compliance to the SMPTE Serial Digital Interface standard, with the ability to support 3G, HD and SD/DVB-ASI video broadcast signals independently on each SERDES channel. The triple rate support is performed without any oversampling technique, consuming the least possible amount of power.
• DSP slices allowing up to 36x36 Multiply and Accumulate blocks in each slice running at 500 MHz. The DSP slices also feature innovative cascadability for implementing wide ALU and adder tree functions without the performance bottlenecks of FPGA logic.
• 800 Mbps DDR3 memory interfaces with built-in read and write leveling.
• 1 Gbps LVDS I/O, with Input Delay blocks, allows interfacing to high performance ADC and DACs.
With these features, the LatticeECP3 FPGA family is well suited for deployment in high-volume, cost- and power-sensitive wireless infrastructure and wireline access equipment, as well as video and imaging applications.
Wireless Design & Development
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