Making Wireless Green: Design Tools & Standards Contribute Too!
A significant challenge for the chip designer is how to communicate the low power requirements and the implementation strategy across multiple design tools at each stage of the design flow.
By Yatin Trivedi, Accellera
Millions of wireless device users rarely think about power unless their gadget is out of power. They use their gadgets all day long, sometimes for a week or a
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Figure 1. UPF based design flow. |
month, and then recharge or replace the battery. The only other time power is important to them is while deciding which gadget to buy; generally a tradeoff between functionality, cost and battery life. This, of course, is possible only because those of us who design such gadgets must worry about power all the time; and, yes, every microwatt counts.
Several engineers who design these products contribute to how much power is used by the device. Starting at the top, the system engineer provides explicit controls to the user such as a power on/off switch and perhaps a standby mode overlaid with it. The software architect applies certain automated heuristics to put the device to sleep after certain duration of inactivity, or cuts off power to music part of hardware while phone logic is active. The chip designer has made clever use of various techniques to support software controlled power management as well as judicious selection of purely hardware techniques such as multiple voltage domains and multiple threshold logic. Of course, one level below in this hierarchy of gadget design is a process engineer who created special low power processes and the corresponding library cells that enable such design techniques.
The scenario described above has one implicit assumption: the availability of low power design tools — the software programs used by the hardware designer to implement, verify and analyze power consumption of the chip. Given the complexity of such chip design, it is understandable that multiple design tools are used to go from concept and specification to its realization in silicon.
In here lies a significant challenge for the chip designer, and that is, how to communicate the low power requirements and the implementation strategy across multiple design tools at each stage of the design flow. This information exchange must be simple and consistent, yet powerful to permit maximum benefit of the underlying process technology and the available software controls, and flexible enough to encourage designer creativity. Of course, the format for such information exchange must be open so that every design tool can extract the power related information relevant to its own flow. Open in this context means not proprietary or restrictive in any legal or business sense, and free of any encumbrances such as royalties or IP rights.
The Electronic Design Automation (EDA) industry, and in particular the electronics standards organization Accellera, answered this low power challenge by bringing together a group of leading wireless chip designers and EDA tool developers. The outcome of this unprecedented collaborative effort was Unified Power Format (UPF). As standards go, UPF has proved to be a standard that was done the right way. This work is now continuing under the IEEE (P1801) for wider scope and broader adoption.
What is UPF?
UPF, written in Tcl, describes the low power intent for design implementation, analysis and verification. It captures the low power design specification from RTL to GDSII, with consistent language throughout the design and verification flow. A UPF specification defines how to create a network to supply power to each design element, how the individual supply nets behave with respect to one another, and how the logic functionality is extended to support dynamic power switching to these logic design elements. By controlling the operating voltages of each supply net and whether the supply nets (and their connected design elements) are turned on or off, the supply network only provides power to the functional areas of the chip needed to complete the computational task in a timely manner.
Combined with the design’s RTL, the UPF file is the input to several tools, e.g., simulators, synthesis tools, formal verification tools and place and route tools. Synthesis tools can read the RTL/UPF design input files and produce a netlist. The UPF file may be reused without change subsequently in the tool flow. A UPF-aware logical equivalence checker can read the full design files and perform checks, including the results of the UPF commands, to ensure equivalence. Place and route tools read both the netlist and the UPF files and produce output, potentially including an output UPF file.
Power design intent can be easily specified over many elements in the design. A UPF specification can be included with the other deliverables of intellectual property (IP) blocks and reused along with the other delivered IP files.
In short, UPF is a robust, flexible standard that addresses chip designers’ power specification needs throughout the design cycle, while allowing them to use low power tools and flows from multiple vendors. It is a prime example of how even companies that are competitors can work together for designing Green Wireless Devices. So next time you look at your gadget and its low power consumption, think of the entire design chain — all the way from Power-On button to what design tools and UPF low power standard are contributing to your gadget’s mean-time-between-recharge!
The UPF standard is available for download at no charge at www.accellera.org. Interested readers can join UPF discussion and follow IEEE P1801 working group progress at p1801@eda.org.
About the Author
Yatin Trivedi is a member of the board of directors, Accellera and
Director, Industry Alliance Programs Magma Design Automation
Wireless Design & Development
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