Direct Digital Synthesis
DDSs built on FPGAs are ideal building blocks for digital communications systems.
Ernest Worthman, Editorial Director
Modern DSPs require high-frequency waveforms without any load on the DSP processors in the system. Direct Digital Synthesizers (DDS) are an efficient and cost-effective method to accomplish this.
In many cases the waveforms generated are modulated by signals from baseband processing. This brief will discuss how DDSs are implemented in transmission systems.
DDS 101
DDSs are comprised one or more digital oscillators. Digital oscillators are simply a set of stored frequencies kept in a lookup table and called by algorithms. Each of these oscillators generates a sine wave that can be modulated in phase, frequency or amplitude.
A single frequency oscillator uses a lookup table with a single. A multi-frequency oscillator's table simply contains multiple table entries. Multi-frequency oscillator tables contain as many stored sine waves as needed, or practical for the design. If more than one oscillator is employed, the development process is the same, and they are usually clocked from a common clock, for synchronization purposes.
For example, to generate a quadrature carrier, two oscillators can be used with a very precise 90° phase separation (see Figure 1). Extrapolating, multiple oscillators can used to generate multiple carriers but the more carriers that are generated, the tighter the control over the phase relationships must be. Typically, each oscillator directly generates an analog output to a DAC.
click the image to enlarge
Figure 1. two oscillators can be used to generate a quadrature carrier
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Let's Generate
For a single oscillator to generate multi-frequencies, the circuit uses a pointer in the sine wave table. As each wave is sampled, the pointer increments one until the end of the table is reached when a reset occurs.
This design approach works well in simple arrays. More complicated DDSs have a few more considerations.
The first consideration is finding a simple way to reset the table pointer. This is where the advantage of using binary numbers comes in — the advantage of automatic rollover.
The design criterion for the the overall size of the table is usually controlled by the application. The more entries, the more primary frequencies are available and the better the resolution. Unfortunately, optimal performance isn't directly linked to large table. There is a trade off in sample number vs. resolution (see the discussion about interpolation a bit later on).
However, there is an advantage as well. One of the nicer things about a binary lookup table is that it doesn't necessarily need to be a full sine wave. It turns out that l/4 is sufficient. However, consider that for smaller tables, the overhead in performing the maths on the pointer and sample is the same as that of large tables. So at some point, reducing the table entries may cause more problems by trading off accuracy for overhead.
Furthermore, in complex DDSs the increment of the pointer cannot be an integer. The reason being that if it was, the frequencies generated would be limited to fractions of the sampling rate.
Therefore, the pointer has to have two elements — an integer part, and a fractional. The integer part is used to address the table, while the fractional part allows us to generate non-integer fractions of the sampling rate. For example if a 32-bit pointer (which is a very popular design for obvious reasons) is combined with a 256-entry table, the configuration is a pointer with eight integer bits, plus 24 fraction bit. Note that, when designing the pointer/table configuration, the more bits defining the fractional part, the greater the frequency resolution.
Now, and as is usually the case, all that glitters in not gold. For non-integer values of the pointer, the sample read from the table will have some error. For example, if the pointer value is exactly 12.4, the read value will be 12 (for 12.6, the read value would be 13). In reality, one looks for a value somewhere between value 12 and 13. This means that the actual value will usually be off slightly, which introduces noise on the output waveform.
A quick note, output noise can be traced to one (or both) of these sources — errors brought about by low -resolution table entries, and errors from reading a value between two table entries. The latter tends to predominate for small tables.
Modulation 101
Frequency modulation (FM) is fairly easy to achieve. Add the modulated signal to the pointer increment value. Phase modulation (PM) is accomplished by adding the modulating signal as an offset to the pointer before performing the table lookup. Finally amplitude modulation (AM) is performed by multiplying the modulating signal with the DDS output.
Summing multiple carriers is similarly efficient. Simply add the outputs of several DDS modules together. Pipelined adders are convenient for this but do add pipeline delays to each channel. Adding too much pipelined overhead will delay some channels more than others. This translated into synchronization instabilities.
Back to the Noise
There are almost as many approaches to noise reduction/cancellation as there are noise sources. One approach to noise elimination at the DDS's output is good old simple filtering. The only problem with that is that most simple filters usually have fixed frequencies. Of course there are lots of variable filters available today, but remember, this is being connected to the DDS — load matters.
Another approach is to add jitter (in the form of random noise) to the frequency and/or phase values used. This has the advantage of not not restricting the DDS to a pre-set frequency range (as is the case with filtering). One thing to think about — combining jitter and fixed frequency filters if the design can accommodate it. This approach allows a high level of noise control.
Finally, depending on whether the DAC will be implemented externally to the FPGA, dictates the approach. or be an integrated within it. If using a device with an integrated DAC, the support library supplied needs to provide a macro for interfacing to the DAC converter(s). If the DAC is external, it will require transmitting the data to other modules using the FIFO interfaces and the macros from the supplied library.
DDSs are becoming a defacto approach to generating signals for modern communications systems. The basic concept is fairly straight-forward. The intricacies come in knowing the trade offs demanded by the applications.
Wireless Design & Development
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