Critical Design & Manufacturing Challenges at 45 nm
Power Management
Brani Buric, Virage Logic
Designs targeting 45 nm will further emphasize requirements for rigorous power savings starting at the system level.
Portable devices — particularly cell phones — have become a driving force behind the rapid acceleration of new silicon-process technologies. A few years ago, a new generation of cell phones was developed at 65 nm technology. At present, all leading cell phone developers are creating yet another new generation of
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devices that target 45 nm or 40 nm process nodes. Increased functionality, better graphics performance, and flexible network and device connectivity such as Bluetooth, 802.11 and WiMAX, are all on the horizon. In addition, longer talk time and longer standby time are key requirements. From a design standpoint, power has emerged as the dominant constraint limiting integration with significant challenges in both active and standby power.
For that reason, designs targeting 45 nm will further emphasize requirements for rigorous power savings starting at the system level. Parallel system architecture results in increased system performance at lower dynamic power consumption. In addition, the reduced performance in the parallel blocks also enables a reduction in gate size, due to lower performance requirements. This further contributes to active power reduction. Implementation of parallel functional structures on the System-on-Chip (SoC) does not come without cost in additional area and power consumption. However, the area reduction expected from the 45 nm process will be offset with increased functionality and area needed for parallel system implementation.
To address active power management at the IP level, the system-level power reduction techniques that will likely be employed must be considered. These techniques include ultra-low supply voltage operation, multiple voltages and power shut down. In addition to supporting the system-level constraints, the IP implementation must achieve the optimum active-power solution with the minimum area degradation.
With 45nm, there is a continuation of exponential growth of standby power. As with active power, standby power must be addressed at the system level.
In addition to traditional challenges such as power, the 45 nm process has exacerbated the problem of on-die process variation, where performance and power are functions of expected yield. At 45 nm, designers will have to trade off area, performance, power and yield in order to meet design and business objectives.
A new generation of physical IP, specifically memories and logic, is now available to address these new requirements.
Power Saving Options
Voltage islands enable non-performance critical blocks in a design to be run at lower supply voltages. Although this results in lower performance, the system architect can tailor the power distribution on the SoC enabling each block to run at its own optimized power and performance level. For example, a designer may decide to use this technique to drive a floating-point processor at a supply voltage that is 30% higher than the core logic. Because a certain function, for example a floating-point processor, is small compared to the overall area of the die, the power specification is met while still achieving the required compute performance.
To connect parts of a design running on different voltages, Virage Logic provides efficient level shifters as an option for its ASAP Logic™ standard cell library product. To save area and simplify design implementation, the company pioneered the use of dual power supply and added level shifters within memories, separating supply voltages between memory arrays and memory periphery. This solution provides the desirable area, power, and performance tradeoff to further reduce the active power of the memory array.
Power gating is a powerful technique that allows the selective power down of functional blocks in a design. Depending on design-specific needs, users may select a fine-grained or coarse- grained power gating architecture. In a fine-grained approach, the supply is controlled for individual cells. In a coarse-grained architecture, power gating cells are used to switch on and off entire functional or IP blocks.
Sleep Mode with State Retention
In many applications, power-down techniques require both the machine states and the memory content be preserved. This means that state retention must be implemented for both flip-flops and memory arrays. Users can implement several different techniques to retain states within their design. If the gates have standby power for the SoC, external flash can be used to store states, although active power is wasted during the load and restore period. Internal SRAM can be used as well, which results in additional power consumption because the memory is required to be always on.
Active Low-Power (ALP) Mode
An alternative solution for saving both active and leakage power is to keep part of a design active but with reduced performance. Virage Logic offers an active low-power mode for logic and memory that can be a cost-effective alternative to voltage islands and other active power-down techniques. In ALP mode, users can deactivate the clock on unselected memory banks. Likewise, a similar technique is applied to the logic and is available as part of the low power option for the ASAP Logic standard cell libraries.
Area/Performance/Power/Yield Tradeoffs
Virage Logic’s SiWare™ Memory offering provides designers with the flexibility to trade off performance and power for yield. This unique capability, proven at the 65 nm process technology, provides users an option to fine-tune performance and power consumption in a function of design volume. Depending on desired manufacturing volumes, users can trade off up to 30% of memory performance by fine-tuning expected manufacturing yield.
Summary
Critical design and manufacturing challenges at 45 nm are driving the need for a new generation of IP that will provide the flexibility and "dash board control to effectively manage the trades of off performance, power, area and yield. All of these requirements must be considered at the architectural level in order to take full advantage of the increased number of transistors used in new process technologies, such as 45 nm.
About the Author
Brani Buric is vice president Product Marketing and Strategic Foundry Relationships. Virage Logic Corporation is located at 47100 Bayside Pkwy., Fremont, CA 94538; 510-360-8000; viragelogic.com.
Virage Logic Corp.
47100 Bayside Parkway
Fremont, CA, 94538
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