Chip-optimization Technology
Cadence announces its manufacturing-aware chip optimization product Cadence® Chip Optimizer, a silicon-proven full-chip optimization system. Cadence Chip Optimizer is used after conventional place and route and before design tape-out. The product uses a 3D space-based optimization approach which models, analyzes and optimizes true shapes and intervening physical spaces. This provides a realistic "map" of the design, and indicates where important optimizations may be made. Shapes and spaces can be positioned in the configuration and location required to correct for sub wavelength, spacing and topological effects.
Cadence Design Systems
Cadence Design Systems Public Relations 2655 Seely Ave. San Jose, CA, 95134
© 2008 Advantage Business Media
|